SH7713 Datasheet, PDF (634/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
2
BRDV2 0
R/W Baud Rate Generator’s Division Ratio Setting (BRDV)
1
BRDV1 0
R/W Set the frequency division ratio BRDV for the output stage
0
BRDV0 0
R/W ^{of the baud rate generator. The final frequency division ratio}
of the baud rate generator is determined by BRPS × BRDV
(maximum 1/1024).
000: Prescalar output × 1/2
001: Prescalar output × 1/4
010: Prescalar output × 1/8
011: Prescalar output × 1/16
100: Prescalar output × 1/32
Note: Other than above is reserved (setting prohibited).
17.3.3 Serial Transmit Data Assign Register (SITDAR)
SITDAR is used to specify the position of the transmit data in a frame (slot number). SITDAR is
initialized by a power-on reset and software reset.
Initial
Bit
Bit Name Value
15
TDLE
0
14 to 12 
All 0
11
TDLA3 0
10
TDLA2 0
9
TDLA1 0
8
TDLA0 0
7
TDRE 0
R/W Description
R/W Transmit Left Channel Data Enable
0: Disables left channel data transmission
1: Enables left channel data transmission
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Transmit Left Channel Data Assigns
R/W Specify the position of left-channel data in transmit frame
R/W ^{as B′0000 to B′1110. Transmit data for the left channel is}
specified in bits SITDL15 to SITDL0 in SITDR.
R/W _{Note: If the TDLA3 to TDLA0 bits are set to B′1111,}
operation is not guaranteed.
R/W Transmit Right Channel Data Enable
0: Disables right channel data transmission
1: Enables right channel data transmission
Rev.1.50 Aug. 30, 2006 Page 594 of 860
REJ09B0288-0150