SH7713 Datasheet, PDF (589/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Initial
Bit
Bit Name Value
4
BRK
0
3
FER
0
Section 16 Serial Communication Interface with FIFO (SCIF)
R/W
R/(W)*
R
Description
Break Detect
In asynchronous mode, indicates that a receive
data break signal has been detected or not.
0: A break signal has not been received
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to BRK after reading BRK = 1
1: A break signal has been received*
[Setting condition]
When data with a framing error is received, followed
by the space “0” level (low level) for at least one
frame length
Note: * When a break is detected, the receive data
(H'00) following detection is not transferred
to SCFRDR. When the break ends and the
receive signal returns to mark “1”, receive
data transfer is resumed.
Framing Error
In asynchronous mode, indicates that there is a
framing error or not in the data read from SCFRDR.
0: There is no framing error in the receive data read
from SCFRDR
[Clearing conditions]
• Power-on reset or manual reset
• When there is no framing error in SCFRDR read
data
1: There is a framing error in the receive data read
from SCFRDR
[Setting condition]
When there is a framing error in SCFRDR read data
Rev.1.50 Aug. 30, 2006 Page 549 of 860
REJ09B0288-0150