SH7713 Datasheet, PDF (162/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
guard-bit parts, the DC bit is set. Even though guard bits are provided in the destination register,
the DC bit always indicates the result of when no guard bits are provided. So, the DC bit is always
set if the guard-bit parts are used for large number representation. Some DC bit generation
examples in overflow mode are shown in figure 3.13.
Example 1
Guard bits
111111111111111111111111
+) 111111111000 0000 0000 0000
111111110111111111111111
Overflow detecting field
Overflow case
Example 2
Guard bits
111111111111111111111111
+) 111111111000 0000 0000 0001
111111111000 0000 0000 0000
Overflow detecting field
Non overflow case
Figure 3.13 DC Bit Generation Examples in Overflow Mode
Signed Greater Than Mode: CS[2:0] = 100: The DC bit indicates whether or not the source 1
data (signed) is greater than the source 2 data (signed) as the result of compare operation PCMP.
This mode is similar to the Negative Value Mode described before, because the result of a
compare operation is a positive value if the source 1 data is greater than the source 2 data.
However, the signed bit of the result shows a negative value if the compare operation yields a
result beyond the range of the destination operand, including the guard-bit parts (called “Over-
range”), even though the source 1 data is greater than the source 2 data. The DC bit is updated
concerning this type of special case in this condition mode. The equation below shows the
definition of getting this condition:
DC = ~ {(Negative ^ Over-range) | Zero}
When the PCMP operation is executed under this condition mode, the result of the DC bit is the
same as the T bit’s result of the CMP/GT operation of the CPU instruction.
Signed Greater Than or Equal Mode: CS[2:0] = 101: The DC bit indicates whether the source
1 data (signed) is greater than or equal to the source 2 data (signed) as the result of compare
operation PCMP. This mode is similar to the Signed Greater Than Mode described before but the
equal case is also included in this mode. The equation below shows the definition of getting this
condition:
DC = ~ (Negative ^ Over-range)
When the PCMP operation is executed under this condition mode, the result of the DC bit is the
same as the T bit’s result of a CMP/GE operation of the SH core instruction.
Rev.1.50 Aug. 30, 2006 Page 122 of 860
REJ09B0288-0150