SH7713 Datasheet, PDF (96/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Table 2.6 Data Transfer Instructions
Instruction
Instruction Code Operation
Privileged
Mode
Cycles T Bit
MOV #imm,Rn
1110nnnniiiiiiii
Imm → Sign extension → Rn 
1

MOV.W @(disp,PC),Rn 1001nnnndddddddd
(disp x 2+PC)→Sign extension 
→ Rn
1

MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp x 4+PC)→Rn

1

MOV Rm,Rn
0110nnnnmmmm0011 Rm→Rn

1

MOV.B Rm,@Rn
0010nnnnmmmm0000 Rm→(Rn)

1

MOV.W Rm,@Rn
0010nnnnmmmm0001 Rm→(Rn)

1

MOV.L Rm,@Rn
0010nnnnmmmm0010 Rm→(Rn)

1

MOV.B @Rm,Rn
0110nnnnmmmm0000 (Rm)→Sign extension→Rn 
1

MOV.W @Rm,Rn
0110nnnnmmmm0001 (Rm)→Sign extension→Rn 
1

MOV.L @Rm,Rn
0110nnnnmmmm0010 (Rm)→Rn

1

MOV.B Rm,@–Rn
0010nnnnmmmm0100 Rn–1→Rn, Rm→(Rn)

1

MOV.W Rm,@–Rn
0010nnnnmmmm0101 Rn–2→Rn, Rm→(Rn)

1

MOV.L Rm,@–Rn
0010nnnnmmmm0110 Rn–4→Rn, Rm→(Rn)

1

MOV.B @Rm+,Rn
0110nnnnmmmm0100 (Rm)→Sign extension→Rn, 
Rm+1→Rm
1

MOV.W @Rm+,Rn
0110nnnnmmmm0101 (Rm)→Sign extension→Rn,

Rm+2→Rm
1

MOV.L @Rm+,Rn
0110nnnnmmmm0110 (Rm)→Rn, Rm+4→Rm

1

MOV.B R0,@(disp,Rn) 10000000nnnndddd R0→(disp+Rn)

1

MOV.W R0,@(disp,Rn) 10000001nnnndddd R0→(disp x 2+Rn)

1

MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd Rm→(disp x 4+Rn)

1

MOV.B @(disp,Rm),R0 10000100mmmmdddd (disp+Rm)→Sign
extension→R0

1

MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp x 2+Rm)→Sign
extension→R0

1

MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd (disp x 4+Rm)→Rn

1

MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rm→(R0+Rn)

1

MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm→(R0+Rn)

1

MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm→(R0+Rn)

1

Rev.1.50 Aug. 30, 2006 Page 56 of 860
REJ09B0288-0150