SH7713 Datasheet, PDF (290/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Bit
Bit Name Initial Value R/W Description
13
BLMSK
0
R/W BL Bit Mask
When the BL bit in SR is set to 1, this bit
specifies whether an NMI interrupt is masked or
not.
0: When the BL bit is set to 1, an NMI interrupt is
masked
1: An NMI interrupt is accepted regardless of the
BL bit setting
12

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
11
IRQ51S
0
R/W IRQn Sense Select
10
IRQ50S
0
9
IRQ41S
0
8
IRQ40S
0
7
IRQ31S
0
6
IRQ30S
0
5
IRQ21S
0
4
IRQ20S
0
3
IRQ11S
0
2
IRQ10S
0
1
IRQ01S
0
0
IRQ00S
0
R/W These bits select whether interrupt request
R/W ^{signals corresponding to pins IRQ5 to IRQ0 are}
detected by a rising edge, falling edge, high
R/W _{level, or low level.}
R/W
Bit 2n+1 Bit 2n
R/W
IRQn1S IRQn0S
R/W
0
0
Interrupt request is
R/W
detected on falling
R/W
edge of IRQn input
R/W
0
1
Interrupt request is
R/W
detected on rising edge
of IRQn input
R/W
1
0
Interrupt request is
detected on low level of
IRQn input
1
1
Interrupt request is
detected on high level
of IRQn input
Legend n=0 to 5
Rev.1.50 Aug. 30, 2006 Page 250 of 860
REJ09B0288-0150