SH7713 Datasheet, PDF (673/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
SCK_SIO
SIOFSYNC
TXD_SIO
Lch.DATA
1 frame
Rch.DATA
RXD_SIO
Slot No.0
Lch.DATA
Slot No.1
Slot No.2
Rch.DATA
Slot No.3
No bit delay
Setting: TRMD = 01, REDG = 1,
FL = 1101 (frame length: 64 bits),
TDLE = 1, TDLA3 to TDLA0 = 0000, TDRE = 1, TDRA3 to TDRA0 = 0010,
RDLE = 1, RDLA3 to RDLA0 = 0001, RDRE = 1, RDRA3 to RDRA0 = 0011,
CD0E = 0, CD0A3 to CD0A0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000
Figure 17.17 Transmission and Reception Timings (16-Bit Stereo Data (2))
16-bit Stereo Data (3): Synchronous pulse method, falling edge sampling, slot No.0 used for left
channel data, slot No.2 used for right channel data, slot No.1 used for control channel 0 data, slot
No.3 used for control channel 1 data, frame length = 128 bits
1 frame
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Lch.DATA
Control
ch.0
Rch.DATA
Control
ch.1
Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7
1 bit delay
Setting: TRMD = 00 or 10, REDG = 0,
TDLE = 1,
TDLA3 to TDLA0 = 0000,
RDLE = 1,
RDLA3 to RDLA0 = 0000,
CD0E = 1,
CD0A3 to CD0A0 = 0001,
FL = 1110 (frame length: 128 bits),
TDRE = 1, TDRA3 to TDRA0 = 0010,
RDRE = 1, RDRA3 to RDRA0 = 0010,
CD1E = 1, CD1A3 to CD1A0 = 0011
Figure 17.18 Transmission and Reception Timings (16-Bit Stereo Data (3))
16-bit Monaural Data (2): Synchronous pulse method, falling edge sampling, request for
secondary FS, slot No.0 used for left channel data, slot No.0 used for control channel 0 data, frame
length = 128 bits
Rev.1.50 Aug. 30, 2006 Page 633 of 860
REJ09B0288-0150