SH7713 Datasheet, PDF (325/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
9.3.4 Break on X/Y-Memory Bus Cycle
1. The break condition on an X/Y-memory bus cycle is specified only in channel B. If the XYE
bit in BBRB is set to 1, the break address and break data on X/Y-memory bus are selected. At
this time, select the X-memory bus or Y-memory bus by specifying the XYS bit in BBRB. The
break condition cannot include both X-memory and Y-memory at the same time. The break
condition is applied to an X/Y-memory bus cycle by specifying L bus/data access/read or
write/word or no specified operand size in bits 7 to 0 in the break bus cycle register B (BBRB).
2. When an X-memory address is selected as the break condition, specify an X-memory address
in the upper 16 bits in BARB and BAMRB. When a Y-memory address is selected, specify a
Y-memory address in the lower 16 bits. Specification of X/Y-memory data is the same for
BDRB and BDMRB.
3. The timing of a data access break for the X memory or Y memory bus to occur is the same as a
data access break of the L bus. For details, see 5 in section 9.3.3, Break on Data Access Cycle.
9.3.5 Sequential Break
1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break
condition matches after a channel A break condition matches. A user break is not generated
even if a channel B break condition matches before a channel A break condition matches.
When channels A and B conditions match at the same time, the sequential break is not issued.
To clear the channel A condition match when a channel A condition match has occurred but a
channel B condition match has not yet occurred in a sequential break specification, clear the
SEQ bit in BRCR to 0.
2. In sequential break specification, the L/I/X/Y bus can be selected and the execution times
break condition can be also specified. For example, when the execution times break condition
is specified, the break condition is satisfied when a channel B condition matches with BETR =
H'0001 after a channel A condition has matched.
Rev.1.50 Aug. 30, 2006 Page 285 of 860
REJ09B0288-0150