SH7713 Datasheet, PDF (637/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Bit
11
10
9
8
7
6 to 4
3
2
1
0
Initial
Bit Name Value R/W Description
CD0A3 0
R/W Control Channel 0 Data Assigns 3 to 0
CD0A2 0
CD0A1 0
CD0A0 0
R/W Specify the position of control channel 0 data in a receive
R/W ^{or transmit frame as B′0000 to B′1110. Transmit data for}
the control channel 0 data is specified in bits SITC015 to
R/W _{SITC00 in SITCR. Receive data for the control channel 0}
data is stored in bits SIRC015 to SIRC00 in SIRCR.
Note: If the CD0A3 to CD0A0 bits are set to B′1111,
operation is not guaranteed.
CD1E
0
R/W Control Channel 1 Data Enable
0: Disables transmission and reception of control channel 1
data
1: Enables transmission and reception of control channel 1
data
—
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
CD1A3 0
R/W Control Channel 1 Data Assigns 3 to 0
CD1A2 0
CD1A1 0
CD1A0 0
R/W Specify the position of control channel 1 data in a receive
R/W ^{or transmit frame as B′0000 to B′1110. Transmit data for}
the control channel 1 data is specified in bits SITC115 to
R/W _{SITC10 in SITCR. Receive data for the control channel 1}
data is stored in bits SIRC115 to SIRC10 in SIRCR.
Note: If the CD1A3 to CD1A0 bits are set to B′1111,
operation is not guaranteed.
Rev.1.50 Aug. 30, 2006 Page 597 of 860
REJ09B0288-0150