SH7713 Datasheet, PDF (87/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Addressing
Mode
Indexed GBR
indirect
Instruction
Format
Effective Address Calculation Method
@(R0,
GBR)
Effective address is sum of register GBR
and R0 contents.
GBR
PC-relative with @(disp:8,
displacement PC)
+
GBR + R0
R0
Effective address is PC with 8-bit
displacement disp added. After disp is
zero-extended, it is multiplied by 2 (word)
or 4 (longword), according to the operand
size. With a longword operand, the lower 2
bits of PC are masked.
PC
&*
H'FFFFFFFC
+
disp
(zero-extended)
×
PC + disp × 2
or
PC &
H'FFFFFFFC
+ disp × 4
PC-relative
disp:8
2/4
*: With longword operand
Effective address is PC with 8-bit
displacement disp added after being sign-
extended and multiplied by 2.
PC
disp
+
(sign-extended)
×
PC + disp × 2
disp:12
2
Effective address is PC with 12-bit
displacement disp added after being sign-
extended and multiplied by 2
PC
disp
+
(sign-extended)
×
PC + disp × 2
2
Calculation
Formula
GBR + R0
Word: PC + disp × 2
Longword:
PC&H'FFFFFFFC +
disp × 4
PC + disp × 2
PC + disp × 2
Rev.1.50 Aug. 30, 2006 Page 47 of 860
REJ09B0288-0150