SH7713 Datasheet, PDF (271/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 7 X/Y Memory
Section 7 X/Y Memory
This LSI has on-chip X-memory and Y-memory which can be used to store instructions or data.
7.1 Features
• Page
There are four pages. The X memory is divided into two pages (pages 0 and 1) and the Y
memory is divided into two pages (pages 0 and 1).
• Memory map
The X/Y memory is located in the logical address space, physical address space, and X-bus
and Y-bus address spaces.
In the logical address space, this memory is located in the addresses shown in table 7.1. These
addresses are included in space P2 (when SR.MD = 1) or Uxy (when SR.MD = 0 and SR.DSP
= 1) according to the CPU operating mode.
Table 7.1 X/Y Memory Logical Addresses
Page
Page 0 of X memory
Page 1 of X memory
Page 0 of Y memory
Page 1 of Y memory
Memory Size (Total Four Pages)
16 kbytes
H′A5007000 to H′A5007FFF
H′A5008000 to H′A5008FFF
H′A5017000 to H′A5017FFF
H′A5018000 to H′A5018FFF
On the other hand, this memory is located in a part of area 1 in the physical address space. When
this memory is accessed from the physical address space, addresses in which the upper three bits
are 0 in addresses shown in table 7.1 are used. In the X-bus and Y-bus address spaces, addresses in
which the upper 16 bits are ignored in addresses of X memory and Y memory shown in table 7.1
are used.
• Ports
Each page has three independent read/write ports and is connected to each bus. The X memory
is connected to the I bus, X bus, and L bus. The Y memory is connected to the I bus, Y bus,
and L bus. The L bus is used when this memory is accessed from the logical address space.
The I bus is used when this memory is accessed from the physical address space. The X bus
and Y bus are used when this memory is accessed from the X-bus and Y-bus address spaces.
Rev.1.50 Aug. 30, 2006 Page 231 of 860
REJ09B0288-0150