SH7713 Datasheet, PDF (897/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Index
Numerics
16-bit/32-bit displacement ........................ 45
A
Absolute addresses ................................... 45
Acceptance priority and test priority ...... 162
Address space identifier (ASID)............. 189
Address transition ................................... 188
Auto-refreshing....................................... 429
Auto-request mode ................................. 477
B
Baud rate generator (BRG)..................... 613
Big endian mode....................................... 42
C
Control by slot position .......................... 620
Control registers ....................................... 32
D
Delayed branching .................................... 44
Double data transfer instructions .............. 94
DSP registers .................................... 77, 106
G
General registers ....................................... 32
Global base register (GBR)....................... 40
I
Instruction length ...................................... 44
IPG settings............................................. 666
L
Literal constant.......................................... 45
Little endian mode .................................... 43
Load/sStore architecture ........................... 44
Low-power consumption state .................. 27
M
Magic packet........................................... 665
MII registers.................................... 662, 663
Modulo register (MOD) ............................ 75
Multiplexed pins ..................................... 719
Multiply and accumulate registers ............ 36
O
On-chip peripheral module request......... 478
E
Exception handling state........................... 27
Exception request of instruction
synchronous type and instruction
asynchronous type .................................. 161
Extension of status register (SR) .............. 74
External request mode .................... 477, 487
P
P0/U0 area................................................. 29
P1 area....................................................... 29
P2 area....................................................... 29
P3 area....................................................... 29
P4 area....................................................... 29
Physical address space ............................ 188
Procedure register ..................................... 36
Rev.1.50 Aug. 30, 2006 Page 857 of 860
REJ09B0288-0150