SH7713 Datasheet, PDF (292/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Bit
Bit Name Initial Value R/W Description
6
BRI0R
0
R
BRI0 Interrupt Request
Indicates whether the BRI0 (SCIF0) interrupt
request is generated.
0: BRI0 interrupt request is not generated
1: BRI0 interrupt request is generated
5
RXI0R
0
R
RXI0 Interrupt Request
Indicates whether the RXI0 (SCIF0) interrupt
request is generated.
0: RXI0 interrupt request is not generated
1: RXI0 interrupt request is generated
4
ERI0R
0
R
ERI0 Interrupt Request
Indicates whether the ERI0 (SCIF0) interrupt
request is generated.
0: ERI0 interrupt request is not generated
1: ERI0 interrupt request is generated
3
DEI3R
0
R
DEI3 Interrupt Request
Indicates whether the DEI3 (DMAC) interrupt
request is generated.
0: DEI3 interrupt request is not generated
1: DEI3 interrupt request is generated
2
DEI2R
0
R
DEI2 Interrupt Request
Indicates whether the DEI2 (DMAC) interrupt
request is generated.
0: DEI2 interrupt request is not generated
1: DEI2 interrupt request is generated
1
DEI1R
0
R
DEI1 Interrupt Request
Indicates whether the DEI1 (DMAC) interrupt
request is generated.
0: DEI1 interrupt request is not generated
1: DEI1 interrupt request is generated
0
DEI0R
0
R
DEI0 Interrupt Request
Indicates whether the DEI0 (DMAC) interrupt
request is generated.
0: DEI0 interrupt request is not generated
1: DEI0 interrupt request is generated
Rev.1.50 Aug. 30, 2006 Page 252 of 860
REJ09B0288-0150