SH7713 Datasheet, PDF (382/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.4.1 Common Control Register (CMNCR)
CMNCR is a 32-bit register that controls the common items for each area. Do not access external
memory other than area 0 until the CMNCR initialization is complete.
Bit
31 to
15
Initial
Bit Name Value R/W

All 0 R
14
BSD
0
R/W
13

0
R
12
MAP
0
R/W
11
BLOCK 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Bus Access Start Timing Specification After Bus
Acknowledge
Specifies the bus access start timing after the external bus
acknowledge signal is received.
0: Starts the external access at the same timing as the
address drive start after the bus acknowledge signal is
received.
1: Starts the external access one cycle following the
address drive start after the bus acknowledge signal is
received.
Reserved
This bit is always read as 0. The write value should always
be 0.
Space Specification
Selects the address map for the external address space.
The address maps to be selected are shown in tables 12.2
and 12.3.
0: Selects address map 1.
1: Selects address map 2.
Bus Lock Bit
Specifies whether or not the BREQ signal is received.
0: Receives BREQ.
1: Does not receive BREQ.
Rev.1.50 Aug. 30, 2006 Page 342 of 860
REJ09B0288-0150