SH7713 Datasheet, PDF (70/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Table 2.1 Logical Address Space
Address Range Name
H'00000000 to P0/U0
H'7FFFFFFF
H'80000000 to P1
H'9FFFFFFF
H'A0000000 to P2
H'BFFFFFFF
H'C0000000 to P3
H'DFFFFFFF
H'E0000000 to P4
H'FFFFFFFF
Mode
Description
Privileged/user mode 2-Gbyte physical space, cacheable, address
translatable
In user mode, only this address space can be
accessed.
Privileged mode
0.5-Gbyte physical space, cacheable
Privileged mode
0.5-Gbyte physical space, non-cacheable
Privileged mode
Privileged mode
0.5-Gbyte physical space, cacheable, address
translatable
0.5-Gbyte control space, non-cacheable
2.2.2 External Memory Space
The LSI uses 29 bits of the 32-bit logical address to access external memory. In this case, 0.5-
Gbyte of external memory space can be accessed. The external memory space is managed in area
units. Different types of memory can be connected to each area, as shown in figure 2.2. For
details, please refer to section 12, Bus State Controller (BSC).
In addition, area 1 in the external memory space is used as an on-chip I/O space where most of
this LSI’s on-chip I/Os are mapped. *¹
Normally, the upper three bits of the 32-bit logical address are masked and the lower 29 bits are
used for external memory addresses.*² For example, address H'00000100 in the P0 area, address
H'80000100 in the P1 area, address H'A0000100 in the P2 area, and address H'C0000100 in the P3
area of the logical address space are mapped into address H’00000100 of area 0 in the external
memory space. The P4 area in the logical address space is not mapped into the external memory
address. If an address in the P4 area is accessed, an external memory cannot be accessed.
Notes: 1. To access an on-chip I/O mapped into area 1 in the external memory space, access the
address from the P2 area which is not cached in the logical address space.
2. If the address translation unit is enabled, arbitrary mapping in page units can be
specified. For details, refer to section 5, Memory Management Unit (MMU).
Rev.1.50 Aug. 30, 2006 Page 30 of 860
REJ09B0288-0150