SH7713 Datasheet, PDF (618/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Error handling
No
ORER = 1?
Yes
Overrun error handling
Clear ORER flag in SCLSR to 0
End
Figure 16.16 Sample Serial Reception Flowchart
In serial reception, the SCIF operates as described below.
1. The SCIF internally initializes in synchronization with the synchronous clock input or output.
2. The SCIF stores receive data in SCRSR in order from LSB to MSB. After reception, the SCIF
checks whether receive data can be transmitted from SCRSR to SCFRDR. If this check is
passed, the SCIF stores the receive data in SCFRDR. If an overrun error is detected by an error
check, following reception can not be performed.
3. If the RDF flag is set to 1 and the RIE bit in SCSCR is set to 1, the SCIF requests a receive-
FIFO-data-full interrupt (RXI). If the ORER flag is set to 1 and the RIE bit or REIE bit in
SCSCR is set to 1, the SCIF requests a break interrupt (BRI).
Rev.1.50 Aug. 30, 2006 Page 578 of 860
REJ09B0288-0150