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SH7713 Datasheet, PDF (102/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 2 CPU
Table 2.10 Branch Instructions
Instruction
Instruction Code Operation
Privileged
Mode
Cycles
BF
label
10001011dddddddd
If T = 0, disp à 2 + PC â PC; 
3/1*
if T = 1, nop
BF/S
label
10001111dddddddd
Delayed branch,

2/1*
if T = 0, disp à 2 + PC â PC;
if T = 1, nop
BT
label
10001001dddddddd
If T = 1, disp à 2 + PC â PC; 
3/1*
if T = 0, nop
BT/S
label
10001101dddddddd
Delayed branch,

2/1*
if T = 1, disp à 2 + PC â PC;
if T = 0, nop
BRA
label
1010dddddddddddd
Delayed branch, disp à 2 + PC 
2
â PC
BRAF Rm
0000mmmm00100011 Delayed branch,Rm + PC â PC 
2
BSR
label
1011dddddddddddd
Delayed branch, PC â PR, disp 
2
à 2 + PC â PC
BSRF Rm
0000mmmm00000011 Delayed branch, PC â PR, Rm 
2
+ PC â PC
JMP
@Rm 0100mmmm00101011 Delayed branch, Rm â PC

2
JSR
@Rm 0100mmmm00001011 Delayed branch, PC â PR, Rm 
2
â PC
RTS
0000000000001011
Delayed branch, PR â PC

2
Note: * One state when the branch is not executed.
T Bit
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Rev.1.50 Aug. 30, 2006 Page 62 of 860
REJ09B0288-0150
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