SH7713 Datasheet, PDF (223/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Process 1
Physical
Memory
Process 1
Physical
Memory
Section 5 Memory Management Unit (MMU)
Process 1
Virtual
Memory
MMU
Physical
Memory
(1)
Process 1
Physical
Memory
Process 2
(2)
Process 1
Process 2
Virtual
Memory
MMU
Physical
Memory
Process 3
Process 3
(3)
(4)
Figure 5.1 MMU Functions
5.1.1 MMU of This LSI
Virtual Address Space: This LSI supports a 32-bit virtual address space that enables access to a
4-Gbyte address space. As shown in figures 5.2 and 5.3, the virtual address space is divided into
several areas. In privileged mode, a 4-Gbyte space comprising areas P0 to P4 are accessible. In
user mode, a 2-Gbyte space of U0 area is accessible, and a 16-Mbyte space of Uxy area is also
accessible if the DSP bit of the SR register is set to 1. Access to any area (excluding the U0 area
and Uxy area) in user mode will result in an address error.
If the MMU is enabled by setting the AT bit of the MMUCR register to 1, P0, P3, and U0 areas
can be used as any physical address area in 1- or 4-kbyte page units. By using an 8-bit address
space identifier, P0, P2, and U0 areas can be increased to up to 256 areas. Mapping from virtual
address to 29-bit physical address can be achieved by the TLB.
Rev.1.50 Aug. 30, 2006 Page 183 of 860
REJ09B0288-0150