SH7713 Datasheet, PDF (693/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.19 Multicast Address Frame Receive Counter Register (MAFCR)
MAFCR is a 32-bit counter that indicates the number of frames received with a specified multicast
address. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter
value is cleared to 0 by a write to this register with any value.
Initial
Bit
Bit Name Value R/W
31 to 0 MAFC31 to All 0
R/W
MAFC0
Description
Multicast Address Frame Count
These bits indicate the count of multicast frames
received.
18.3.20 IPG Register (IPGR)
IPGR sets the IPG (Inter Packet Gap). This register must not be changed while the transmitting
and receiving functions of the EtherC mode register (ECMR) are enabled. (For details, refer to
section 18.4.6, Operation by IPG Setting.)
Initial
Bit
Bit Name Value R/W
31 to 5 
All 0
R
4 to 0 IPG4 to H′13
R/W
IPG0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Inter Packet Gap
Sets the IPG value every 4-bit time.
H′00: 20-bit time
H′01: 24-bit time
:
:
H′13: 96-bit time (Default)
:
:
H′1F: 144-bit time
Rev.1.50 Aug. 30, 2006 Page 653 of 860
REJ09B0288-0150