SH7713 Datasheet, PDF (250/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Memory Management Unit (MMU)
Start
CPU address
error
No
Yes
Address error?
No
VPNs Match?
No
Yes
No
SH = 0 and
(MMUCR.SV = 0 or
SR.MD = 0)?
Yes
VPNs
and ASIDs
Match?
Yes
TLB Miss
Exception
User Mode
V=1?
Yes
User or
Privileged?
No
TLB Invalid
Exception
Privileged Mode
PR?
00/01 10
W _R/W?
R
11
R/W? ^W
R
No
PR?
01/11
00/10
W _R/W?
R/W? ^W
R
R
D=1?
TLB Protection
Violation Exception
Yes
TLB Protection
Violation Exception
Initial page Write
Exception
No (Non-Cacheable)
Memory
Access
C=1?
Yes (Cacheable)
Cache
Access
Figure 5.13 MMU Exception Generation Flowchart
Rev.1.50 Aug. 30, 2006 Page 210 of 860
REJ09B0288-0150