SH7713 Datasheet, PDF (204/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
Current
Exception Type Instruction Exception Event
Exception Process Vector
Priority*¹ Order
at BL=1 Code Vector Offset
General exception Completed User breakpoint
2
events
(Data break, I-BUS
(asynchronous)
break)
5
Ignored H'1E0 H'00000100
DMA address error
2
6
Retained H'5C0 H'00000100
General interrupt Completed Interrupt requests
3
requests
(asynchronous)
—*²
Retained —*³
H'00000600
Notes: 1. Priorities are indicated from high to low, 1 being the highest and 3 the lowest.
A reset has the highest priority. An interrupt is accepted only when general exceptions
are not requested.
2. For details on priorities in multiple interrupt sources, refer to section 8, Interrupt
Controller (INTC).
3. If an interrupt is accepted, the interrupt source register (EXPEVT) is not changed. The
interrupt source code is specified in interrupt source register 2 (EXPEVT2). For details,
refer to section 8, Interrupt Controller (INTC).
4. If one of these exceptions occurs in a specific part of the repeat loop, a specific code
and vector offset are specified.
5. These exception codes are valid when the MMU is used.
Rev.1.50 Aug. 30, 2006 Page 164 of 860
REJ09B0288-0150