SH7713 Datasheet, PDF (243/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Memory Management Unit (MMU)
Virtual address 1 H'00000000 → physical address H'00000C00
Virtual address 2 H'00000C00 → physical address H'00000C00
Virtual address 1 is recorded in cache entry H'000, and virtual address 2 in cache entry H'0C0.
Since two virtual addresses are recorded in different cache entries despite the fact that the physical
addresses are the same, memory inconsistency will occur as soon as a write is performed to either
virtual address.
Consequently, the following restrictions apply to the recording of address translation information
in TLB entries.
1. When address translation information whereby a number of 1-kbyte page TLB entries are
translated into the same physical address is recorded in the TLB, ensure that the VPN [n:10]
are the same.
2. When address translation information whereby a number of 4-kbyte page TLB entries are
translated into the same physical address is recorded in the TLB, ensure that the VPN [n:12] is
the same.
3. Do not use the same physical addresses for address translation information of different page
sizes.
The above restrictions apply only when performing accesses using the cache.
Note: When multiple items of address translation information use the same physical memory to
provide for future SuperH RISC engine family expansion, ensure that the VPN bits 20 to
10 are the same.
Rev.1.50 Aug. 30, 2006 Page 203 of 860
REJ09B0288-0150