SH7713 Datasheet, PDF (23/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 20 Pin Function Controller (PFC).........................................................719
20.1 Overview............................................................................................................................ 719
20.2 Register Configuration....................................................................................................... 720
20.3 Register Descriptions ......................................................................................................... 721
20.3.1 Port A Control Register (PACR) .......................................................................... 721
20.3.2 Port B Control Register (PBCR)........................................................................... 722
20.3.3 Port C Control Register (PCCR)........................................................................... 723
20.3.4 Ethernet Controller Pin Control Register (PETCR).............................................. 724
Section 21 I/O Ports ...........................................................................................727
21.1 Overview............................................................................................................................ 727
21.2 Register Descriptions ......................................................................................................... 727
21.2.1 Port A Data Register (PADR)............................................................................... 727
21.2.2 Port B Data Register (PBDR) ............................................................................... 728
21.2.3 Port C Data Register (PCDR) ............................................................................... 730
Section 22 User Debugging Interface (H-UDI) .................................................731
22.1 Features.............................................................................................................................. 731
22.2 Input/Output Pins ............................................................................................................... 732
22.3 Register Descriptions ......................................................................................................... 733
22.3.1 Bypass Register (SDBPR) .................................................................................... 733
22.3.2 Instruction Register (SDIR) .................................................................................. 733
22.3.3 Boundary Scan Register (SDBSR) ....................................................................... 734
22.3.4 ID Register (SDID)............................................................................................... 741
22.4 Operation ........................................................................................................................... 742
22.4.1 TAP Controller ..................................................................................................... 742
22.4.2 Reset Configuration .............................................................................................. 743
22.4.3 TDO Output Timing ............................................................................................. 743
22.4.4 H-UDI Reset ......................................................................................................... 744
22.4.5 H-UDI Interrupt .................................................................................................... 744
22.5 Boundary Scan ................................................................................................................... 745
22.5.1 Supported Instructions .......................................................................................... 745
22.5.2 Points for Attention............................................................................................... 746
22.6 Usage Notes ....................................................................................................................... 746
22.7 Advanced User Debugger (AUD)...................................................................................... 746
Section 23 List of Registers ...............................................................................747
23.1 Register Addresses
(by functional module, in order of the corresponding section numbers)............................ 748
Rev.1.50 Aug. 30, 2006 Page xxiii of xl