SH7713 Datasheet, PDF (656/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
(a) Falling-edge sampling
SCK_SIO
(a) Rising-edge sampling
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Reception timing
Transmission timing
Figure 17.4 SIOF Transmit/Receive Timing
Reception timing
Transmission timing
17.4.3 Transfer Data Format
The SIOF performs the following transfer.
• Transmit/receive data: Transfer of 8-bit data/16-bit data/16-bit stereo data
• Control data: Transfer of 16-bit data (uses the specific register as interface)
Transfer Mode: The SIOF supports the following four transfer modes as listed in table 17.3. The
transfer mode can be specified by the TRMD1 and TRMD0 bits in SIMDR.
Table 17.3 Serial Transfer Modes
Transfer Mode
Slave mode 1
Slave mode 2
Master mode 1
Master mode 2
SIOFSYNC
Synchronous pulse
Synchronous pulse
Synchronous pulse
L/R
Bit Delay
One bit
One bit
One bit
No
Control Data
Slot position
Secondary FS
Slot position
Not supported
Frame Length: The length of the frame to be transferred by the SIOF is specified by the FL3 to
FL0 bits in SIMDR. Table 17.4 shows the relationship between the settings of the FL3 to FL0 bits
and frame length.
Rev.1.50 Aug. 30, 2006 Page 616 of 860
REJ09B0288-0150