SH7713 Datasheet, PDF (397/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W
5 to 2 
All 0 R
1
HW1
0
R/W
0
HW0
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5AWCR
Initial
Bit
Bit Name Value R/W Description
31 to 19 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
18
WW2
0
R/W Number of Write Access Wait Cycles
17
WW1
0
16
WW0
0
R/W Specify the number of cycles that are necessary for write
R/W ^access.
000: The same cycles as WR3 to WR0 setting (read access
wait)
001: 0 cycle
010: 1 cycle
011: 2 cycles
15 to 13 
All 0 R
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev.1.50 Aug. 30, 2006 Page 357 of 860
REJ09B0288-0150