SH7713 Datasheet, PDF (595/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
7
RTRG1
0
R/W Receive FIFO Data Number Trigger 1 and 0
6
RTRG0
0
R/W Set the number of receive data bytes that sets the
RDF flag in SCFSR.
The RDF flag is set when the number of receive data
bytes in SCFRDR is equal to or greater than the
trigger set number shown in below.
Asynchronous mode Clock synchronous mode
00: 1
00: 1
01: 4
01: 2
10: 8
10: 8
11: 14
11: 14
5
TTRG1
0
R/W Transmit FIFO Data Number Trigger 1 and 0
4
TTRG0
0
R/W Set the number of remaining transmit data bytes that
sets the TDFE flag in SCFSR.
The TDFE flag is set when, as the result of a transmit
operation, the number of transmit data bytes in
SCFTDR is equal to or below the trigger set number
shown in below.
00: 8 (8)
01: 4 (12)
10: 2 (14)
11: 0 (16)
Note: The values in parentheses are the number of
empty bytes in SCFTDR when the flag is set.
3
MCE
0
R/W Modem Control Enable
Enables modem control signals CTS and RTS. This
bit is valid only in asynchronous mode.
0: Modem signal disabled*
1: Modem signal enabled
Note: * CTS is fixed at active 0 regardless of the input
value, and RTS is also fixed at 0.
Rev.1.50 Aug. 30, 2006 Page 555 of 860
REJ09B0288-0150