SH7713 Datasheet, PDF (21/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

17.4.8 Interrupts............................................................................................................... 628
17.4.9 Transmission and Reception Timing .................................................................... 630
17.5 Usage Notes ....................................................................................................................... 635
Section 18 Ethernet Controller (EtherC)............................................................637
18.1 Features.............................................................................................................................. 637
18.2 Input/Output Pins ............................................................................................................... 638
18.3 Register Descriptions ......................................................................................................... 639
18.3.1 Software Reset Register (ARSTR) ....................................................................... 640
18.3.2 EtherC Mode Register (ECMR)............................................................................ 641
18.3.3 EtherC Status Register (ECSR) ............................................................................ 644
18.3.4 EtherC Interrupt Permission Register (ECSIPR) .................................................. 645
18.3.5 PHY Interface Register (PIR) ............................................................................... 646
18.3.6 MAC Address High Register (MAHR) ................................................................ 647
18.3.7 MAC Address Low Register (MALR).................................................................. 647
18.3.8 Receive Frame Length Register (RFLR) .............................................................. 648
18.3.9 PHY Status Register (PSR)................................................................................... 649
18.3.10 Transmit Retry Over Counter Register (TROCR) ................................................ 649
18.3.11 Delayed Collision Detect Counter Register (CDCR)............................................ 650
18.3.12 Lost Carrier Counter Register (LCCR)................................................................. 650
18.3.13 Carrier Not Detect Counter Register (CNDCR) ................................................... 650
18.3.14 CRC Error Frame Receive Counter Register (CEFCR)........................................ 651
18.3.15 Frame Receive Error Counter Register (FRECR)................................................. 651
18.3.16 Too-Short Frame Receive Counter Register (TSFRCR)....................................... 651
18.3.17 Too-Long Frame Receive Counter Register (TLFRCR)....................................... 652
18.3.18 Residual-Bit Frame Receive Counter Register (RFCR) ....................................... 652
18.3.19 Multicast Address Frame Receive Counter Register (MAFCR)........................... 653
18.3.20 IPG Register (IPGR)............................................................................................. 653
18.3.21 TSU Counter Reset Register (TSU_CTRST) ....................................................... 654
18.3.22 Transmit Frame Counter Register (Normal Transmission Only) (TXNLCR) ...... 654
18.3.23 Transmit Frame Counter Register (Normal and Error Transmission)
(TXALCR)............................................................................................................ 655
18.3.24 Receive Frame Counter Register (Normal Reception Only) (RXNLCR)............. 655
18.3.25 Receive Frame Counter Register (Normal and Error Reception) (RXALCR)...... 656
18.4 Operation ........................................................................................................................... 656
18.4.1 Transmission......................................................................................................... 656
18.4.2 Reception .............................................................................................................. 658
18.4.3 MII Frame Timing ................................................................................................ 660
18.4.4 Accessing MII Registers ....................................................................................... 662
18.4.5 Magic Packet Detection ........................................................................................ 665
Rev.1.50 Aug. 30, 2006 Page xxi of xl