SH7713 Datasheet, PDF (287/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Bit
Bit Name Initial Value R/W Description
15

0
14

0
13

0
R/W These bits set the priority level for each interrupt
R/W ^{source in 4-bit units. For details, see table 8.5,}
Interrupt Sources and IPRA to IPRI.
R/W
12

0
R/W
11

0
R/W
10

0
R/W
9

0
R/W
8

0
R/W
7

0
R/W
6

0
R/W
5

0
R/W
4

0
R/W
3

0
R/W
2

0
R/W
1

0
R/W
0

0
R/W
Table 8.5 Interrupt Sources and IPRA to IPRI
Register
Bits 15 to 12
Bits 11 to 8
Bits 7 to 4
IPRA
TMU0
TMU1
TMU2
IPRB
WDT
REF
Reserved*
IPRC
IRQ3
IRQ2
IRQ1
IPRD
Reserved*
Reserved*
IRQ5
IPRE
DMAC (1)
SCIF0
SCIF1
IPRF
Reserved*
DMAC (2)
Reserved*
IPRG
E-DMAC
Reserved*
Reserved*
IPRH
Reserved*
Reserved*
Reserved*
IPRI
Reserved*
Reserved*
SIOF1
Note: * Always read as 0. The write value should always be 0.
Bits 3 to 0
RTC
Reserved*
IRQ0
IRQ4
Reserved*
Reserved*
Reserved*
SIOF0
Reserved*
Rev.1.50 Aug. 30, 2006 Page 247 of 860
REJ09B0288-0150