SH7713 Datasheet, PDF (506/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
15
DM1
0
R/W Destination Address Mode
14
DM0
0
R/W Specify whether the DMA destination address is
incremented, decremented, or left fixed. (In single address
mode, the DM1 and DM0 bits are ignored when data is
transferred to an external device with the DACK.)
00: Fixed destination address (setting prohibited in 16-byte
transfer)
01: Destination address is incremented (+1 in byte transfer,
+2 in word transfer, +4 in longword transfer, +16 in 16-
byte transfer)
10: Destination address is decremented (–1 in byte transfer,
–2 in word transfer, –4 in longword transfer; setting
prohibited in 16-byte transfer)
11: Reserved (setting prohibited)
13
SM1
0
R/W Source Address Mode
12
SM0
0
R/W Specify whether the DMA source address is incremented,
decremented, or left fixed. (In single address mode, the
SM1 and SM0 bits are ignored when data is transferred
from an external device with the DACK.)
00: Fixed source address (setting prohibited in 16-byte
transfer)
01: Source address is incremented (+1 in byte transfer, +2
in word transfer, +4 in longword transfer, +16 in 16-byte
transfer)
10: Source address is decremented (–1 in byte transfer, –2
in word transfer, –4 in longword transfer; setting
prohibited in 16-byte transfer)
11: Reserved (setting prohibited)
Rev.1.50 Aug. 30, 2006 Page 466 of 860
REJ09B0288-0150