SH7713 Datasheet, PDF (232/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Memory Management Unit (MMU)
Bit
31 to 9
8
7, 6
5, 4
3
2
1
Bit Name

Initial
Value
All 0
SV
0

All 0
RC
All 0

0
TF
0
IX
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Single virtual memory mode
0: Multiple virtual memory mode
1: Single virtual memory mode
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Random counter
A 2-bit random counter that is automatically updated
by hardware according to the following rules in the
event of an MMU exception.
When a TLB miss exception occurs, all of TLB entry
way corresponding to the virtual address at which
the exception occurred are checked. If all ways are
valid, 1 is added to RC; if there is one or more
invalid way, they are set by priority from way 0, in
the order way 0, way 1, way 2, way 3. In the event
of an MMU exception other than a TLB miss
exception, the way which caused the exception is
set in RC.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W TLB flush
Write 1 to flush the TLB (clear all valid bits of the
TLB to 0). When they are read, 0 is always returned.
R/W Index mode
0: VPN bits 16 to 12 are used as the TLB index
number.
1: The value obtained by EX-ORing ASID bits 4 to 0
in PTEH and VPN bits 16 to 12 is used as the
TLB index number.
Rev.1.50 Aug. 30, 2006 Page 192 of 860
REJ09B0288-0150