SH7713 Datasheet, PDF (845/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 Electrical Characteristics
CKIO
A25 to A0
A12/A11*¹
Td1 Td2 Td3
Td4
Tr
Tc1 Tc2
Tc3
Tc4
Tde
t_AD1
t_AD1
Row
address
t_AD1
t_AD1
Column
address
t_AD1
t_AD1
Read command
t_AD1
(1 to 4)
t_AD1
t_AD1
coRmeamdaAnd
t_AD1
CSn
RD/WR
RAS
CAS
DQMxx
t_CSD1
t_RWD1
t_RASD1 t_RASD1
t_CASD1
t_DQMD1
D31 to D0
t_BSD
BS
t_CSD1
t_RWD1
t_CASD1
t_DQMD1
t_RDS2 t_RDH2
t_BSD
t_RDS2 t_RDH2
CKE
t_DACD
(High)
t_DACD
DACKn*²
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 24.24 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4),
(Auto Precharge, CAS Latency = 2, TRCD = 1 Cycle, TRP = 2 Cycle)
Rev.1.50 Aug. 30, 2006 Page 805 of 860
REJ09B0288-0150