SH7713 Datasheet, PDF (655/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
(a) Synchronous pulse
1 frame
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
(b) L/R
First bit data (MSB)
1-bit delay
1 frame
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
First bit of left
channel data (MSB)
No delay
1/2 frame length
First bit of right
channel data (MSB)
1/2 frame length
Figure 17.3 Serial Data Synchronization Timing
Transmit/Receive Timing: The TXD_SIO transmission timing and RXD_SIO reception timing
relative to the SCK_SIO signal can be set as the sampling timing in the following two ways. The
transmit/receive timing is set using the REDG bit in SIMDR. In slave mode 1 and slave mode 2,
only falling-edge sampling is available.
• Falling-edge sampling
• Rising-edge sampling
Figure 17.4 shows the transmit/receive timing.
Rev.1.50 Aug. 30, 2006 Page 615 of 860
REJ09B0288-0150