SH7713 Datasheet, PDF (426/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Table 12.8 8-Bit External Device/Big Endian Access and Data Alignment
Data Bus
Strobe Signals
Operation
D31 to D23 to D15 to D7 to WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0),
D24 D16 D8 D0
DQMUU DQMUL DQMLU DQMLL
Byte access at 0    Data 


Assert
7 to 0
Byte access at 1    Data 


Assert
7 to 0
Byte access at 2    Data 


Assert
7 to 0
Byte access at 3    Data 


Assert
7 to 0
Word
1st time    Data 


Assert
access at 0 at 0
15 to 8
2nd    Data 


Assert
time at
7 to 0
1
Word
1st time    Data 


Assert
access at 2 at 2
15 to 8
2nd    Data 


Assert
time at
7 to 0
3
Longword 1st time    Data 


Assert
access at 0 at 0
31 to
24
2nd    Data 


Assert
time at
23 to
1
16
3rd
   Data 


Assert
time at
15 to 8
2
4th
   Data 


Assert
time at
7 to 0
3
Rev.1.50 Aug. 30, 2006 Page 386 of 860
REJ09B0288-0150