SH7713 Datasheet, PDF (465/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
CKIO
A25 to A0
A12/A11*¹
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Td1
Td2
Td3
Td4
Tp
Tpw
Tr
Tc1
Tc2
Tc3
Tc4
Tde
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.21 Burst Read Timing (Bank Active, Different Row Addresses)
Rev.1.50 Aug. 30, 2006 Page 425 of 860
REJ09B0288-0150