SH7713 Datasheet, PDF (120/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
• Example 2: Repeat loop consisting of three instructions
LDRS RptStart +4
; Sets (repeat detection instruction
address + 4) to the RS register
LDRE RptStart +4
; Sets (repeat detection instruction
address + 4) to the RE register
SETRC #4
; Sets the number of repetitions (4) to
the RC[11:0] bits of the SR register
; If RE-RS==0 during SETRC instruction
execution, the repeat loop is regarded
as three-instruction repeat.
RptDtct: instr0
; An instruction prior to the Repeat
start instruction is regarded as a
repeat detection instruction.
RptStart: instr1
; [Repeat start instruction]
Instr2
;
RptEnd: instr3
; [Repeat end instruction]
• Example 3: Repeat loop consisting of two instructions
LDRS RptStart +6
; Sets (repeat detection instruction
address + 6) to the RS register
LDRE RptStart +4
; Sets (repeat detection instruction
address + 4) to the RE register
SETRC #4
; Sets the number of repetitions (4) to
the RC[11:0] bits of the SR register
; If RE-RS==-2 during SETRC instruction
execution, the repeat loop is regarded
as two-instruction repeat.
RptDtct: instr0
; An instruction prior to the Repeat
start instruction is regarded as a
repeat detection instruction.
RptStart: instr1
; [Repeat start instruction]
RptEnd: instr2
; [Repeat end instruction]
Rev.1.50 Aug. 30, 2006 Page 80 of 860
REJ09B0288-0150