SH7713 Datasheet, PDF (414/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
14
TED3
0
R/W Delay from Address to RD or WE Assert
13
TED2
0
R/W Specify the delay time from address output to RD or WE
12
TED1
0
R/W ^{assert in PCMCIA interface.}
11
TED0
0
R/W ^{0000: 0.5 cycle}
0001: 1.5 cycles
0010: 2.5 cycles
0011: 3.5 cycles
0100: 4.5 cycles
0101: 5.5 cycles
0110: 6.5 cycles
0111: 7.5 cycles
1000: 8.5 cycles
1001: 9.5 cycles
1010: 10.5 cycles
1011: 11.5 cycles
1100: 12.5 cycles
1101: 13.5 cycles
1110: 14.5 cycles
1111: 15.5 cycles
Rev.1.50 Aug. 30, 2006 Page 374 of 860
REJ09B0288-0150