SH7713 Datasheet, PDF (65/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Classification Symbol
I/O
Ethernet
controller
(EtherC)
RX-CLK0
I
RX-DV0
I
ERXD03 to
I
ERXD00
MDC0
O
MDIO0
I/O
WOL0
O
LNKSTA0
I
EXOUT0
O
ARBUSY
O
Serial
CTS1,
I
communication _CTS0
interface with
FIFO (SCIF1/0) _RTS1,
O
RTS0
Section 1 Overview and Pin Function
Name
Function
MAC receive
clock
Timing reference pin (clock) for
RX-DV0, RX-ER0, and ERXD03
to ERXD00. For a connection
example, refer to section 18,
Ethernet Controller (EtherC).
MAC receive
data valid
This pin indicates that valid
receive data is on ERXD03 to
ERXD00. For a connection
example, refer to section 18,
Ethernet Controller (EtherC).
MAC receive
data
4-bit receive data pins. For a
connection example, refer to
section 18, Ethernet Controller
(EtherC).
MAC
management
data clock
Reference clock pin for
information transfer via MDIO. For
a connection example, refer to
section 18, Ethernet Controller
(EtherC).
MAC
management
data I/O
Bidirectional pin for exchanging
management information. For a
connection example, refer to
section 18, Ethernet Controller
(EtherC).
MAC Wake-On- This pin indicates that a Magic
LAN
Packet has been received.
MAC link status Link state input pin from the PHY-
LSI
MAC general- External output pin
purpose
external output
Bus release
request
This pin outputs a bus release
request when the amount of data
in the receive FIFO reaches the
threshold.
SCIF1/0
transmission
clear
Modem control pins
SCIF1/0
Modem control pins
transmit request
Rev.1.50 Aug. 30, 2006 Page 25 of 860
REJ09B0288-0150