SH7713 Datasheet, PDF (306/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
9.2 Register Descriptions
The user break controller has the following registers. For details on register addresses and access
sizes, refer to section 23, List of Registers.
• Break address register A (BARA)
• Break address mask register A (BAMRA)
• Break bus cycle register A (BBRA)
• Break address register B (BARB)
• Break address mask register B (BAMRB)
• Break bus cycle register B (BBRB)
• Break data register B (BDRB)
• Break data mask register B (BDMRB)
• Break control register (BRCR)
• Execution times break register (BETR)
• Branch source register (BRSR)
• Branch destination register (BRDR)
• Break ASID register A (BASRA)
• Break ASID register B (BASRB)
9.2.1 Break Address Register A (BARA)
BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition
in channel A.
Bit
31 to 0
Bit Name
BAA31 to
BAA 0
Initial
Value R/W
All 0 R/W
Description
Break Address A
Store the address on the LAB or IAB specifying break
conditions of channel A.
Rev.1.50 Aug. 30, 2006 Page 266 of 860
REJ09B0288-0150