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| SH7713 Datasheet, PDF (866/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 24 Electrical Characteristics
CKIO
A25 to A0
A12/A11*1
Tp
Tpw
Trr
Trc
Trc
Trc
tAD3
tAD3
tAD3
tAD3
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
tCSD2
tCSD2
tCSD2
tCSD2
tRWD2
tRWD2
tRASD2
tRASD2
tRASD2
tRASD2
tCASD2
tCASD2
(Hi-Z)
tRWD2
BS
CKE
(High)
DACKn*2
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 24.45 Synchronous DRAM Auto-Refresh Timing
(TRP = 2 Cycle, Low-Frequency Mode)
Rev.1.50 Aug. 30, 2006 Page 826 of 860
REJ09B0288-0150
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