SH7713 Datasheet, PDF (303/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
Section 9 User Break Controller
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and stop timing
in the case of instruction fetch.
9.1 Features
The UBC has the following features:
1. The following break comparison conditions can be set.
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and then channel B match with break conditions,
but not in the same bus cycle).
• Address
Compares 40 bits configured of the ASID and addresses 32 bits: the ASID can be selected
either all-bit comparison or all-bit mask. Comparison bits are maskable in 1-bit units; user can
mask addresses at lower 12 bits (4-k page), lower 10 bits (1-k page), or any size of page, etc.
One of the four address buses (logic address bus (LAB), internal address bus (IAB),
X-memory address bus (XAB), and Y-memory address bus (YAB)) can be selected.
• Data
Only on channel B, 32-bit maskable.
One of the four data buses (L-bus data (LDB), I-bus data (IDB), X-memory data bus (XDB)
and Y-memory data bus (YDB)) can be selected.
• Bus cycle
Instruction fetch or data access
• Read/write
• Operand size
Byte, word, and longword
2. A user-designed user-break condition exception processing routine can be run.
UBCS300B_000020020900
Rev.1.50 Aug. 30, 2006 Page 263 of 860
REJ09B0288-0150