SH7713 Datasheet, PDF (648/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Initial
Bit Bit Name Value R/W
8
RDREQE 0
R/W
7 to 5 —
All 0 R
4
FSERRE 0
R/W
3
TFOVRE 0
R/W
2
TFUDRE 0
R/W
1
RFUDRE 0
R/W
0
RFOVRE 0
R/W
Description
Receive Data Transfer Request Enable
0: Disables interrupts due to receive data transfer requests
1: Enables interrupts due to receive data transfer requests
(receive interrupt)
Reserved
These bits are always read as 0. The write value should
always be 0.
Frame Synchronization Error Enable
0: Disables interrupts due to frame synchronization error
1: Enables interrupts due to frame synchronization error
(error interrupt)
Transmit FIFO Overrun Enable
0: Disables interrupts due to transmit FIFO overrun
1: Enables interrupts due to transmit FIFO overrun (error
interrupt)
Transmit FIFO Underrun Enable
0: Disables interrupts due to transmit FIFO underrun
1: Enables interrupts due to transmit FIFO underrun (error
interrupt)
Receive FIFO Underrun Enable
0: Disables interrupts due to receive FIFO underrun
1: Enables interrupts due to receive FIFO underrun (error
interrupt)
Receive FIFO Overrun Enable
0: Disables interrupts due to receive FIFO overrun
1: Enables interrupts due to receive FIFO overrun (error
interrupt)
Rev.1.50 Aug. 30, 2006 Page 608 of 860
REJ09B0288-0150