SH7713 Datasheet, PDF (533/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
13.5 Usage Note
When using the DMAC, note the following:
Note on Using TEND Pin:
If a DMA transfer is performed under one of the conditions described below and, after completion
of the transfer, retransfer is performed on the same channel, the TEND pin is asserted once in the
first DMA transfer in retransfer when the retransfer condition satisfies (1) DACK is output in a
dual address mode read cycle (with the AM bit in CHCR cleared to 0) and the DMA transfer
source address (SAR) is in external memory space or (2) in single address mode.
Conditions:
• DACK is output in a dual address mode read cycle (with the AM bit in CHCR cleared to 0)
and the DMA transfer source address (SAR) is in external memory space.
• DACK is output in a dual address mode write cycle (with the AM bit in CHCR set to 1) and
the DMA transfer destination address (DAR) is in external memory space.
• Single address mode
Method of Avoidance:
Perform a dummy DMA transfer under one of the settings below. After start of a dummy DMA
transfer, clear all bits in the DMA channel control register (CHCR) of the corresponding channel
to suspend the dummy DMA transfer forcibly.
• DACK is output in a dual address mode read cycle (with the AM bit in CHCR cleared to 0)
and the DMA transfer source address (SAR) is in external memory space.
• DACK is output in a dual address mode write cycle (with the AM bit in CHCR set to 1) and
the DMA transfer destination address (DAR) is in external memory space.
Rev.1.50 Aug. 30, 2006 Page 493 of 860
REJ09B0288-0150