SH7713 Datasheet, PDF (729/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.2.12 Receiving Method Control Register (RMCR)
RMCR is a 32-bit readable/writable register that specifies the control method for the RE bit in
ECMR when a frame is received. This register must be set during the receiving-halt state.
Initial
Bit
Bit Name Value R/W Description
31 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
RNC
0
R/W Receive Enable Control
Sets whether to continue frame reception.
0: Upon completion of reception of one frame, the E-
DMAC writes receive status to the descriptor and
clears the RR bit in EDRRR to 0
1: Upon completion of reception of one frame, the E-
DMAC writes (writes back) receive status to the
descriptor. In addition, the E-DMAC reads the next
descriptor and prepares for the reception of the
next frame
Rev.1.50 Aug. 30, 2006 Page 689 of 860
REJ09B0288-0150