SH7713 Datasheet, PDF (674/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
(a) When control channel is not transferred
1 frame
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Lch.DATA
Slot No.0 Slot
No.1
Slot
No.2
Slot
No.3
Slot
No.4
1bit delay
LSB = 0 (Secoundary FS request)
(b) When control channel is transferred
1 frame
1/2 frame
Slot
No.5
Slot
No.6
1/2 frame
Slot
No.7
SCK_SIO
SIOFSYNC
Normal FS
Secondary FS
Normal FS
TXD_SIO
RXD_SIO
Lch.DATA
Control
channel 0
Slot
No.0
Slot
No.1
Slot
No.2
Slot
No.3
Slot
No.0
Slot
No.1
Slot
No.2
Slot
No.3
1bit delay
LSB = 1 (Secoundary FS request)
Setting: TRMD = 01
REDG = 0,
FL = 1110 (frame length: 128 bits),
TDLE = 1,
TDLA3 to TDLA0 = 0000, TDRE = 0,
TDRA3 to TDRA0 = 0000,
RDLE = 1,
RDLA3 to RDLA0 = 0000, RDRE = 0,
RDRA3 to RDRA0 = 0000,
CD0E = 1,
CD0A3 to CD0A0 = 0000, CD1E = 0,
CD1A3 to CD1A0 = 0000
Figure 17.19 Transmission and Reception Timings (16-Bit Monaural Data (2))
Rev.1.50 Aug. 30, 2006 Page 634 of 860
REJ09B0288-0150