SH7713 Datasheet, PDF (400/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W
18
WW2
0
R/W
17
WW1
0
R/W
16
WW0
0
R/W
15 to 13 
All 0 R
12
SW1
0
R/W
11
SW0
0
R/W
Description
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for write
access.
000: The same cycles as WR3 to WR0 setting (read
access wait)
001: 0 cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address, CSn Assertion to
RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev.1.50 Aug. 30, 2006 Page 360 of 860
REJ09B0288-0150