SH7713 Datasheet, PDF (721/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)
EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual
bits in the EtherC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the
corresponding bit.
Initial
Bit
Bit Name Value
31

0
30
TWBIP
0
29 to 27 
All 0
26
TABTIP
0
25
RABTIP 0
24
RFCOFIP 0
23
ADEIP
0
22
ECIIP
0
21
TCIP
0
R/W Description
R Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Write-Back Complete Interrupt Enable
0: Write-back complete interrupt is disabled
1: Write-back complete interrupt is enabled
R Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Transmit Abort Detection Interrupt Enable
0: Transmit abort detection interrupt is disabled
1: Transmit abort detection interrupt is enabled
R/W Receive Abort Detection Interrupt Enable
0: Receive abort detection interrupt is disabled
1: Receive abort detection interrupt is enabled
R/W Receive Frame Counter Overflow Interrupt Enable
0: Receive frame counter overflow interrupt is disabled
1: Receive frame counter overflow interrupt is enabled
R/W Address Error Interrupt Enable
0: Address error interrupt is disabled
1: Address error interrupt is enabled
R/W EtherC Status Register Interrupt Enable
0: EtherC status interrupt is disabled
1: EtherC status interrupt is enabled
R/W Frame Transmit Complete Interrupt Enable
0: Frame transmit complete interrupt is disabled
1: Frame transmit complete interrupt is enabled
Rev.1.50 Aug. 30, 2006 Page 681 of 860
REJ09B0288-0150