SH7713 Datasheet, PDF (150/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Initial
Bits Bit Name Value
5
N
0
4
V
0
3 to 1 CS2 to All 0
CS0
0
DC
0
R/W
R/W
R/W
R/W
R/W
Function
Negative Bit
Indicates that the operation result is negative, or that
operand 1 is smaller than operand 2
1: Operation result is negative, or operand 1 is
smaller than operand 2
Overflow Bit
Indicates that the operation result has overflowed
1: Operation result has overflowed
DC Bit Status Selection
Designate the mode for selecting the operation result
status to be set in the DC bit
000: Carry/borrow mode
001: Negative value mode
010: Zero mode
011: Overflow mode
100: Signed greater mode
101: Signed greater than or equal to mode
110: Reserved (setting prohibited)
111: Reserved (setting prohibited)
DSP Status Bit
Sets the status of the operation result in the mode
designated by the CS bits
0: Designated mode status has not occurred (false)
1: Designated mode status has occurred
Indicates the operation result by carry or borrow
regardless of the CS bit status after the PADDC or
PSUBC instruction has been executed.
Rev.1.50 Aug. 30, 2006 Page 110 of 860
REJ09B0288-0150