SH7713 Datasheet, PDF (177/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
3.5.11 Overflow Protection
The S bit in SR is effective for any arithmetic operations executed in the DSP unit, including the
SH's standard multiply and MAC operations. The S bit in SR is used as the overflow protection
enable bit. The arithmetic operation overflows when the operation result exceeds the range of
two’s complement representation without guard-bit parts. Table 3.31 shows the definition of
overflow protection for fixed-point arithmetic operations, including fixed-point signed by signed
multiplication described in section 3.5.7, Fixed-Point Multiply Operation. Table 3.32 shows the
definition of overflow protection for integer arithmetic operations. The lower word of the
saturation value of the integer arithmetic operation is don’t care. Lower word value cannot be
guaranteed.
When the overflow protection is effective, overflow never occurs. So, the V bit is cleared, and the
DC bit is also cleared when the overflow mode is selected by the CS[2:0] bits.
Table 3.31 Definition of Overflow Protection for Fixed-Point Arithmetic Operations
Sign
Positive
Negative
Overflow Condition
Result > 1 – 2^–31
Result < –1
Fixed Value
1 – 2^–31
–1
Hex Representation
00 7FFF FFFF
FF 8000 0000
Table 3.32 Definition of Overflow Protection for Integer Arithmetic Operations
Sign
Overflow Condition
Positive
Result > 2¹⁵ – 1
Negative
Result < –2¹⁵
Note: * means don't care.
Fixed Value
2¹⁵ – 1
–2¹⁵
Hex Representation
00 7FFF ****
FF 8000 ****
Rev.1.50 Aug. 30, 2006 Page 137 of 860
REJ09B0288-0150