SH7713 Datasheet, PDF (107/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Instruction Code
Fx: 0000
Fx: 0001
Fx: 0010
Fx: 0011 to 1111
MSB
LSB MD: 00
MD: 01
MD: 10
MD: 11
0010
Rn
Rm
01MD
MOV.B Rm, @–
Rn
0010
Rn
Rm
10MD
TST
Rm, Rn
0010
Rn
Rm
11MD
CMP/STRRm, Rn
0011 Rn Rm 00MD CMP/EQ Rm, Rn
CMP/HS Rm, Rn CMP/GERm, Rn
0011 Rn Rm 01MD DIV1 Rm, Rn
DMULU.L Rm,Rn CMP/HI Rm, Rn CMP/GT Rm, Rn
0011 Rn Rm 10MD SUB Rm, Rn
SUBC Rm, Rn SUBV Rm, Rn
0011 Rn Rm 11MD ADD Rm, Rn
DMULS.L Rm,Rn ADDC Rm, Rn ADDV Rm, Rn
0100 Rn Fx
0000 SHLL Rn
DT
Rn
SHAL Rn
0100 Rn Fx
0001 SHLR Rn
CMP/PZ Rn
SHAR Rn
0100 Rn Fx
0010 STS.L MACH, @– STS.L MACL, @– STS.L PR, @–Rn
Rn
Rn
0100 Rn 00MD 0011 STC.L SR, @–Rn STC.L GBR, @–Rn STC.L VBR, @– STC.L SSR, @–
Rn
Rn
0100 Rn 01MD 0011 STC.L SPC, @–Rn
0100 Rn 10MD 0011 STC.L
STC.L
STC.L
STC.L
R0_BANK, @–Rn R1_BANK, @–Rn R2_BANK, @–Rn R3_BANK, @–Rn
0100 Rn 11MD 0011 STC.L
STC.L
STC.L
STC.L
R4_BANK, @–Rn R5_BANK, @–Rn R6_BANK, @–Rn R7_BANK, @–Rn
0100 Rn Fx
0100 ROTL Rn
ROTCL Rn
0100 Rn Fx
0101 ROTR Rn
CMP/PL Rn
ROTCR Rn
0100 Rm Fx
0110 LDS.L
@Rm+, MACH
LDS.L @Rm+,
MACL
LDS.L @Rm+, PR
0100 Rm 00MD 0111 LDC.L @Rm+, SR LDC.L @Rm+,
GBR
LDC.L @Rm+,
VBR
LDC.L @Rm+,
SSR
0100 Rm 01MD 0111 LDC.L @Rm+,
SPC
0100 Rm 10MD 0111 LDC.L
LDC.L
LDC.L
LDC.L
@Rm+, R0_BANK @Rm+, R1_BANK @Rm+, R2_BANK @Rm+, R3_BANK
0100 Rm 11MD 0111 LDC.L
LDC.L
LDC.L
LDC.L
@Rm+, R4_BANK @Rm+, R5_BANK @Rm+, R6_BANK @Rm+, R7_BANK
0100 Rn Fx
1000 SHLL2 Rn
SHLL8 Rn
SHLL16 Rn
Rev.1.50 Aug. 30, 2006 Page 67 of 860
REJ09B0288-0150