SH7713 Datasheet, PDF (561/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 15 Realtime Clock (RTC)
Bit
Bit Name Initial Value R/W Description
6
—
0
R
Reserved
5
—
0
R
These bits are always read as 0. The write value
should always be 0.
4
CIE
0
R/W Carry Interrupt Enable Flag
When the carry flag (CF) is set to 1, the CIE bit
enables interrupts.
0: A carry interrupt is not generated when the CF
flag is set to 1
1: A carry interrupt is generated when the CF flag
is set to 1
3
AIE
0
R/W Alarm Interrupt Enable Flag
When the alarm flag (AF) is set to 1, the AIE bit
allows interrupts.
0: An alarm interrupt is not generated when the
AF flag is set to 1
1: An alarm interrupt is generated when the AF
flag is set to 1
2
—
0
R
Reserved
1
—
0
R
These bits are always read as 0. The write value
should always be 0.
0
AF
0
R/W Alarm Flag
The AF flag is set to 1 when the alarm time set in
an alarm register (only registers with the ENB bit
of the corresponding alarm registers and YAEN
bit in RCR3 set to 1) matches the clock and
calendar time. This flag is cleared to 0 when 0 is
written, but holds the previous value when 1 is to
be written.
0: Clock/calendar and alarm register have not
matched.
Clearing condition: When 0 is written to AF
1: Clock/calendar and alarm register have
matched.
Setting condition: Clock/calendar and alarm
register have matched (only registers with the
ENB bit and YAEN bit in RCR3 set to 1)
Rev.1.50 Aug. 30, 2006 Page 521 of 860
REJ09B0288-0150