SH7713 Datasheet, PDF (508/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
4
TS1
0
R/W Transfer Size
3
TS0
0
R/W Specify the size of data to be transferred.
Select the size of data to be transferred when the source
or destination is an on-chip peripheral module register of
which transfer size is specified.
00: Byte size
01: Word (two bytes) size
10: Longword (four bytes) size
11: 16-byte (four longwords) size
2
IE
0
R/W Interrupt Enable
Specifies whether or not an interrupt request is generated
to the CPU at the end of the DMA transfer. Setting this bit
to 1 generates an interrupt request (DEI) to the CPU
when the TE bit is set to 1.
0: Interrupt request is disabled
1: Interrupt request is enabled
1
TE
0
R/(W)* Transfer End Flag
The TE bit is set to 1 when data transfer ends when
DMATCR becomes to 0.
The TE bit is not set to 1 in the following cases.
• DMA transfer ends due to an NMI interrupt or DMA
address error before DMATCR becomes 0.
• DMA transfer is ended by clearing the DE bit and
DME bit in the DMA operation register (DMAOR).
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
interrupted
1: DMA transfer ends by the specified count (DMATCR =
0)
[Clearing condition]
Writing 0 after reading 1 from this bit
Rev.1.50 Aug. 30, 2006 Page 468 of 860
REJ09B0288-0150